1. Field of the Invention
This invention relates to the field of latch circuits. More particularly, this invention relates to latch circuits including a data retention latch.
2. Description of the Prior Art
Static leakage currents are becoming a significant factor in the total power consumption of CMOS process devices with sizes less than 100 nanometers. Accordingly, techniques to reduce leakage current are becoming more significant. One way to stop leakage currents is to switch off the power supply to the circuit when the circuit is idle. Another method of leakage current reduction is to disconnect the CMOS logic gates from the power supply when the system is idle, using high-threshold PMOS “Header” transistors or high-threshold NMOS “footer” transistors placed between the logic gates and the Vdd and Vss power supplies. This technique is usually referred to as multi-threshold CMOS (MTCMOS).
Whilst the above techniques do reduce the power consumption due to leakage currents when the circuit is idle, they suffer from the disadvantage that whether the power supply is switched off or isolated from the circuit, the stored logic state of sequential circuits (latches and flip-flops) is lost. There are latch circuit designs that maintain the stored state when most of their circuitry is powered down by including a small number of devices which are powered from a separate permanently enabled power supply. Such devices are sometimes referred to as “retention flops”. One known type of retention flop has an additional latch, separate from the usual master and slave latches, that maintains the stored state when the rest of the circuit is powered down. This type of latching circuit is sometimes called a “balloon flop” and the additional data retaining latch is known as a “balloon latch”.
Whilst retention latches have advantages in reducing static leakage current and avoiding a loss of state such that processing can be rapidly resumed, they do suffer from disadvantages in themselves. Control signals need to be provided to control the saving of state into the balloon (data retention) latch and to restore that saved state back into the main latch. These control signals must be widely distributed throughout the system concerned since a comparatively high number of latches are typically present and these need to be supplied with the appropriate save and restore control signals. The additional circuit layout, area, power consumption and other overhead associated with these high fan out save and restore control signals is a significant disadvantage.